This course introduces the principles of advanced computer architecture. The student is expected to enter this class with a basic understanding of computer architecture, along with assembly language. Building upon these fundamentals, the student will learn advanced architectural techniques for making computers run orders of magnitude faster than would be possible from technological improvements alone.
John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, third edition, Morgan Kaufmann Publishers, 2003.
Prof. Stan Birchfield
207A Riggs Hall
656-5912
stb clemson.edu (insert @ symbol)
Office Hours: Tuesday 2-3pm, Wednesday 2-3pm, or by appointment
Yi Jiang (Johnny)
yij clemson.edu (insert @ symbol)
654-2794 (home)
20% homework, 25% midterm #1, 25% midterm #2, 30% final
Homeworks will be due on Thursdays, at the beginning of class. No late homeworks will be accepted. Please do homeworks neatly so the grader can read them (engineering paper or typing is recommended). Students are encouraged to work together on homeworks, but each student must turn in his/her own work.
technology/architectural trends and history
performance evaluation
instruction sets
pipelining
structural, data, and control hazards
instruction level parallelism
branch prediction
dynamic scheduling and hardware prediction
superscalar issue
cache memory
thread-level parallelism
| Week | Dates | Assignments | Topics | Readings |
| 1 | 8/21 | Introduction | 1.1-1.3, 1.11, 2.11, 2.16 | |
| 2 | 8/26, 8/28 | HW1 out | Performance | 1.5-1.10 |
| 3 | 9/2, 9/4 | HW1 due, HW2 out | Instruction sets | 2.1-2.3, 2.12; COD 3.1-3.8 * |
| 4 | 9/9, 9/11 | HW2 due, HW3 out | Datapath design I | COD 4.5, 5.1-5.3, B.1-B.5 |
| 5 | 9/16, 9/18 | HW3 due, HW4 out | Datapath design II | COD 5.4-5.6, B.6 |
| 6 | 9/23, 9/25 | HW4 due | Datapath design II | COD 5.4-5.6, B.6 |
| 7 | 9/30, 10/2 | Review and midterm | ||
| 8 | 10/7, 10/9 | HW5 out | Pipelining I | Appendix A.1-A.3; (COD 6.1-6.6) |
| 9 | 10/14, 10/16 | HW5 due | Pipelining II | Appendix A.4-A5 |
| 10 | 10/23 | HW6 out | Pipelining II | Appendix A.4-A.5 |
| 11 | 10/28, 10/30 | HW6 due, HW7 out | dynamic scheduling | Appendix A.8, 3.1-3.3 |
| 12 | 11/4, 11/6 | HW7 due | Review and midterm | |
| 13 | 11/11, 11/13 | HW8 out | dynamic hardware prediction | 3.4-3.5 |
| 14 | 11/18, 11/20 | HW8 due, HW9 out | Superscalar, speculation, compiler-based ILP | 3.6-3.9, 4.1-4.6 |
| 15 | 11/25 | HW9 due | Memory hierarchies | 5.1-5.3; (COD 7.1-7.3) |
| 16 | 12/2, 12/4 | Memory hierarchies and review | 5.4-5.7 | |
| 12/6 | Final exam, 6:30-9:30pm |
* COD refers to David A. Patterson and John L. Hennessy, Computer organization and design : the hardware/software interface, Morgan Kaufmann Publishers, 1998. (on reserve at the library: QA76.9.C643 H46)
Course website: http://www.ces.clemson.edu/~stb/ece429
Additional material may be placed on MyCLE site
“As members of the Clemson University community, we have inherited Thomas Green Clemson’s vision of this institution as a “high seminary of learning.” Fundamental to this vision is a mutual commitment to truthfulness, honor, and responsibility, without which we cannot earn the trust and respect of others. Furthermore, we recognize that academic dishonesty detracts from the value of a Clemson degree. Therefore, we shall not tolerate lying, cheating, or stealing in any form.”
“It is University policy to provide, on a flexible and individualized basis, reasonable accommodations to students who have disabilities. Students are encouraged to contact Student Disability Services to discuss their individual needs for accommodation.”