• Pad size: 0.5 mm × 0.5 mm × 0.017 mm
• Cathode/Anode: 0.5 mm × 0.1 mm × 0.5 mm
• Plate: 0.5 mm × 0.7 mm × 0.05 mm
• PCB Dielectric: 5.6 mm × 5 mm × 0.1 mm
• Gap between the plates: 0.1 mm
• Capacitor size: 1005
• Power/Ground planes: 5.6 mm × 5 mm × 0.017 mm

Setup:
The structure was drawn using the model editor. Then, using the simulation file builder, the model file was opened and the simulation default parameters were utilized. The build file and run option was then selected.

ibm_smtind.zip

1. Materials
   • Copper modeled as a PEC
   • Capacitor and PCB dielectric modeled as FR4
   • Vias modeled as boxes instead of cylinders
   • Shorting blocks between plates
2. Simulation
   • Output charge data selected to obtain a graphical representation
   • Disabled capacitance solution because it won't work with this setup
   • Ran simulation in the background due to execution time

• What adjustments were made in generating the vias?
  
  The vias in this model were generated with a square rather than a circle. The software models cylinders as a group of rectangles so it was easier to go ahead and model the vias as a box instead of a cylinder. The PCB modeling with this structure was difficult to realize in software. There is no intuitive way to cut the holes that are needed for power and ground plane connections.
• Was the capacitor added in as a part instead of drawn in place?
  
  The capacitor was drawn first and saved as a part. The ability to draw components separately and add them later as pieces of the puzzle is very convenient and also speeds up the modeling time.