ECE 201 - Lab 3

 

Combinational Circuits:  Parity Generation and Detection

 

PURPOSE

To familiarize the student with combination circuits by studying methods of parity generation and detection.

 

EQUIPMENT

ECE 201 Lab Kit & Digi-Trainer

Simulation Software

 

REQUIREMENTS

 

 

PROCEDURE

 

Section 1 – Parity Generator

 

In this part of the lab, we will design and build circuits to generate and detect odd parity for three-bit words. Our parity generator circuit will take three input bits (x, y, and z) and produce one output bit (P). The truth table for this parity generator is shown below:

 

x y z     P

0 0 0     1

0 0 1     0

0 1 0     0

0 1 1     1

1 0 0     0

1 0 1     1

1 1 0     1

1 1 1     0

 

Use the Karnaugh Map to produce an MSOP representation of this function by grouping the 1's of the function.

 

       P =  ________________________________________

 

?

How many 2 input AND and OR gates and how many inverters would be required to implement the equation for P above? (Remember, it takes two 2-input gates to make one 3-input gate)

 

ANDs -                                               ORs -                                       NOTs -

 

This circuit can be implemented with the chips in your lab kit, but it would leave only one OR gate and no AND gates to implement our entire parity detection circuit. (Not to mention that it would be a pain to wire up!). Can we simplify this function in order to simplify the hardware? This is one of those examples where you see why engineers can't be replaced by computers (yet).

The K-map guarantees us MSOP form, but that's not the simplest form for this problem. Neither is the MPOS form we'd get from grouping the zeroes. (Try it and see.)  Notice that the Karnaugh map shows a checkerboard pattern (every other square).  When this pattern exists, the function can be implemented in either an XOR or XNOR operation. The equation obtained for P can be simplified using the properties of Boolean algebra as follows:

P = (x'y' + xy) z' + (x'y + xy') z  

   = (x Å y)' z' + (x Å y) z

 

If we let A = x Å y then, we have

 

P = A'z' + Az = (A Åz)' = (x Å y Å z)'

Therefore, we can implement P with a three-variable XNOR gate. Of course, we don't have a three-input XNOR gate in our lab kits, but we can easily build one from two XOR gates (7486) and single inverter (Recall that XOR is associative, like AND or OR, so that ( x Åy) Åz = x Å y Å z).

 

 

Use Digital Works to create a macro of your parity generator circuit. 

 

Wire up the circuit on your breadboard and test its function.

Section 2– Parity Detector

Next, we need to implement a Parity Detector circuit.  It will have four inputs:  the three information bits, x, y, and z and the newly created parity bit, P.  It will have one output bit, the error, E, which will be high whenever there is a parity error.

 

Fill in the value for E in the truth table for this circuit below. Remember, E will be 1 whenever P is not the correct odd parity bit for the values of x, y, and z:

 

x y z P   E         x y z P   E

0 0 0 0            1 0 0 0  

0 0 0 1            1 0 0 1  

0 0 1 0            1 0 1 0  

0 0 1 1            1 0 1 1  

0 1 0 0            1 1 0 0  

0 1 0 1            1 1 0 1  

0 1 1 0            1 1 1 0  

0 1 1 1            1 1 1 1  

 

Now, find an MSOP equation for E using the Karnaugh map below:

 

         E =  _____________________________________

 

Once again, you'll notice that this equation would be a nuisance to wire up since we cannot form any groups on the map.  And, once again, we notice the familiar checkerboard pattern.

 

If we look back at our truth table, we'll notice that E is true whenever there is an even number of 1's in the four input variables (just as P was 1 whenever there was an even number of 1 's in the input in the table for our generator circuit). Once again, we can implement this function as an XNOR of the four input variables,

E = (x Å y Å z  Å P )’

Because of this property, XNOR is also known as the even function, and XOR is also known as the odd function.  If we changed our truth table so that our output was true whenever there was an odd number of 1s, the resulting function would be an XOR, and the Karnaugh map would still look like a checkerboard, but the first one would be in square 0001 instead of 0000.

 

Create your parity detection circuit using the equation for E above as a macro in Digital Works with four inputs and 1 output and verify its function.  To test your simulation, embed your generator and detector macros in the same circuit as shown in the figure below:

 

 

Figure 1. Parity Generator and Detector

 

 

Wire up your circuit on your breadboard. This will require three more XOR gates and one more inverter.  You should have two 7486 chips in your kit. Connect your parity generator to your parity detector and verify that it works correctly.

 

?

How might you change the circuit above to simulate a communication where a single bit error may be introduced to one of the four inputs to the parity detector?