## Printed Circuit Board Power Bus Decoupling Questions## 1. What is the best strategy for connecting decoupling capacitors to a printed circuit board?The answer to this question depends on the type of board you are trying to decouple and what you are trying to accomplish by adding decoupling capacitors. For the moment we will assume that your goal is to supply all of the current needed for the proper operation of the active component while minimizing noise on the power bus. With this in mind, there are three possible decoupling strategies depending on the type of power bus you have. - PCB without power planes
- PCB with closely spaced (<.3 mm) power and ground planes
- PCB with power and ground planes that are not closely spaced
In all cases, the following guidelines apply: - It is the capacitor's impedance that determines how much current it can supply for a given change in its voltage. The lower the impedance, the better.
- At low frequencies, the capacitor's impedance is determined by its capacitance value. More capacitance is better.
- At high frequencies, the capacitor's impedance is determined by its connection inductance plus its internal inductance. Generally speaking, smaller capacitor packages tend to have lower internal inductance and lower connection inductance. The smaller the package, the better.
- Most printed circuit board designs have one or more large-valued bulk capacitors to reduce the impedance of the power bus at low frequencies and several low-inductance capacitors to reduce the impedance of the power bus at high frequencies.
- It is particularly important to minimize the connection inductance of capacitors that are intended to reduce power bus noise at high frequencies.
## References:
Power Bus Decoupling on Multilayer Printed Circuit
Boards (pdf - 821 kB)
An Experimental Investigation of 4-Layer Printed
Circuit Board Decoupling (pdf - 363 kB)
Simulation and Measurement for Decoupling on
Multilayer PCB DC Power Buses (pdf - 478
kB)
An Experimental Procedure for Characterizing
Interconnects to the DC Power Bus on a Multilayer
PCB (pdf - 242 kB)
Designing Power Bus Decoupling for CMOS Devices
(pdf - 366 kB)
Experimental Evaluation of Power Bus Decoupling on
a 4-layer Printed Circuit Board (pdf - 365
kB)
Quantifying Decoupling Capacitor Location (pdf -
902 kB) "Quantifying SMT Decoupling Capacitor Placement in
DC Power-Bus Design for Multilayer PCBs," (pdf -
406 kB) "Reducing Power Bus
Impedance at Resonance with Lossy Components," (pdf - 370 kB)
Decoupling Strategies for Printed Circuit Boards
without Power Planes (pdf - 240 kB) |